Processor-Memory Power Shifting for Multi-Core Systems

Maximum power consumption is an important consideration in server design, as the total power envelope affects cooling costs and can limit performance. One approach to limiting total power is power shifting, managing power budgets among system sub-components to meet an overall total constraint. In this paper, we investigate processor-memory power shifting on a multi-threaded, 32-core commercial server. Our results use several benchmark suites to cover a wide range of workload characteristics from CPU-intensive to memory intensive, illustrating power shifting’s performance and power trade-offs on a large-scale commercial server. First, we use a feedback loop to dynamically adjust frequency and voltage (DVFS) to the highest possible frequency that does not exceed the power envelope, tracking fluctuations in workload activity. Second, we implement a published power-shifting algorithm that monitors component power use to allocate separate power budgets for processors and memory. The processor budget is enforced by dynamic voltage and frequency scaling (DVFS); the memory power budget is enforced by memory throttling. We found that under moderate power constraints, both algorithms performed well, with only minor performance degradation. Under a more tightly constrained budget, both algorithms reduced performance by approximately 5-25%, and the singleactuator approach in this study had the surprising outcome of a slight performance advantage, simply because it did not waste allocated budget. Overall, we show how power shifting improves power efficiency, supporting peak performance under favorable power conditions and strategically managing performance in power-limited situations.